Thin film transistors (TFTs) are used in a variety of applications such as pixel switching transistors in active matrix displays on glass substrates, or low-cost electronic circuits, such as radiofrequency identification (RFID) tags. A conventional TFT in a top-gate architecture according to the prior art is shown in FIG. 1A. On a substrate 1 source-and drain electrodes 2 with channel length L are defined by photolithographic patterning. A semiconducting active layer island 3 is defined by depositing the active semiconductor as a continuous layer and subsequently patterning it. A gate dielectric layer 4 is then deposited. Finally a gate electrode 5 is deposited and patterned on top in another photolithography step.
The switching performance and speed of the TFT is critically determined by the parasitic capacitances Cgs and Cgd between the gate electrode and the source/drain electrodes, respectively. This is determined by the channel width W, channel length L, and geometric overlap s between gate and source/drain electrodes and should be kept as small as possible. For optimum performance for a given channel length L it is important that the gate electrode only covers the channel itself, and does not overlap significantly with the source and drain electrodes themselves. In order to minimize s so-called self-aligned gate processes can be used where the patterning is performed in such a way that the gate electrode is automatically aligned with respect to the channel without requiring precise alignment between the source-drain pattern and the gate pattern.
In order to achieve cost reduction and enable manufacturing on flexible substrate, such as plastic substrates, manufacturing processes based on alternative patterning techniques such as solution-based printing and laser ablation have been used. These are particularly applicable for material sets based on organic semiconductors, such as solution-processible polymer semiconductors or small molecule organic semiconductors, or solution-processible inorganic semiconductors, such as inorganic nanoparticles or nanowires. One of the common drawbacks of such manufacturing techniques is that the realization of self-aligned electrodes and small linewidths is much more challenging.
Another draw back of the large overlap area that is present with non-self-aligned gate electrodes (including printed gate electrodes) is that the device is susceptible to pinhole or particle defects in the gate dielectric located in the active area of the device. The gate dielectric needs to be thin in order to enable a large ON current of the TFT, but the larger the overlap area of the device the more likely it is that a defect will cause a short between electrodes on the gate and the source-drain level. This is particularly important on flexible plastic substrate for which typical substrate quality is not as high, and particle defect density not as low as on conventional glass substrates.
There are several low-cost manufacturing methods in the prior art for gate patterning. These include both selective laser ablation patterning (SLAP) and direct-write printing processes.
According to one low-cost manufacturing method in the prior art gate patterning is achieved by selective laser ablation patterning (SLAP). This technique is disclosed in an earlier patent, (see GB0513915.9), the entire content of which is included in the present application by way of reference, allowing patterning by laser ablation of metallic layers on upper layers of a device without radiation induced damage of lower, underlying layers.
The technique of SLAP is a method of producing fine features of a device using short pulse lasers for the fabrication of thin film transistor (TFT) structures. This technique incorporating laser ablation uses a single shot per imaging area of a short pulse laser to pattern layers of metallic material on top of underlying layers in order to produce fine features of a TFT device. An example is the patterning of a gold gate electrode of a top-gate organic TFT with underlying gate dielectric, active semiconductor and conducting source-drain electrode layers. This technique may be performed without destroying or substantially degrading the performance of these sensitive elements, such as the semiconductor layer and the source-drain electrodes. This is due to the short pulse length allowing all of the energy of an ultra-short laser beam to enter the material and to be absorbed within the layer to be ablated which will result in the act of ablation before any substantial thermalization actually occurs, that can lead to degradation/ablation of underlying layer. In addition, this technique may be used to finely tune the source and drain electrode formation after a coarser laser ablation process, resulting in the substantial elimination of burring edges that could lead to electrical shorts.
The SLAP technique is capable of producing linewidths on the order of 10-20 μm or lower, i.e., significantly narrower than what is achievable with printing techniques. For top exposure accurate alignment of the SLAP patterned layer with respect to underlying layers requires precise alignment of the laser ablation mask with respect to the previously patterned layer, which is challenging to do on a distorted, flexible substrate.
According to an alternative low-cost TFT manufacturing method in the prior art (see for example, US20050274986) a thin film transistor is manufactured by a direct-write printing process. On a substrate a first source electrode and a second drain electrode are patterned by inkjet printing followed by deposition of semiconducting and dielectric layers. The channel length L between the source and drain electrodes is defined, for example, by printing the two electrodes sufficiently far apart from each other or by using surface energy patterns to direct the flow of ink on the substrate (US20050274986). In this way channel lengths of several microns or tens of microns can be defined. In US20050151820—the content of which is included in the present document by way of reference—in order to realize shorter channel lengths a self-aligned printing (SAP) process was demonstrated (FIG. 8). The surface 48 of the first source electrode 47 is prepared such that it is repulsive to the ink of the second electrode 49. As a result the ink is repelled by the surface of the first electrode, flows off the pattern of the first electrode, and dries in close proximity but not in physical contact with the first electrode. In this way it is possible to define channel lengths on the order of 100 nm by inkjet printing.
After deposition of the semiconductor layer 50 and dielectric 51 the gate electrode 52 is printed subsequently and has a relatively large linewidth of typically 50-100 μm due to the difficulties of dispensing small liquid volumes with present day printing technologies. Therefore, for both micron scale channel lengths as well as for submicrometer channel length fabricated by techniques such as SAP the geometric overlap s between the source/drain and gate electrodes is very large, and the parasitic capacitance of such a TFT is large in spite of the small channel length. In the case of submicrometer source-drain electrodes fabricated by SAP this parasitic capacitance limits the switching speed of the TFTs, and prevents making full use of the short channel length realized in these devices.
Methods for realizing self-aligned printed gates have been proposed in WO05022664, but these rely on confining the ink of the gate electrode to the region above the channel and require precise control of ink and surface properties in order to confine a large ink volume onto a narrow line. In the case of micrometer or even submicrometer channel length this is very challenging.